The present invention relates to integrated circuit devices and methods of operating same, and more particularly to integrated circuit signal buffers and methods of operating integrated circuit signal buffers.
Conventional signal buffers frequently include CMOS inverter stages that drive an output signal line rail-to-rail, from a lower reference potential (e.g., GND) to a power supply voltage (e.g., Vdd). Attempts to use such signal buffers at higher power supply voltages frequently require the development and use of MOS transistors that can support correspondingly higher gate-to-drain, gate-to-source and drain-to-source voltages without failure. Accordingly, signal buffers are frequently designed to include MOS transistors that can support the maximum anticipated power supply voltage for a designated application. Unfortunately, the characteristics of MOS transistors capable of supporting higher voltages may not be acceptable for other applications which do not require operation under relatively high voltages, including applications in other portions of an integrated circuit chip that operate at lower internal power supply voltages. To address these issues, level shifting circuits have been developed to xe2x80x9cinsulatexe2x80x9d MOS transistors from higher external power supply voltages by reducing on-chip voltages. However, such circuits may not allow for changes in an external power supply voltage to occur to meet a particular application and/or may not adequately shield all MOS transistors from high voltages.
Thus, notwithstanding the use of such level shifting circuits, there continues to be need to develop signal buffers that have excellent performance characteristics and can be operated at a plurality of different power supply voltages without failure.
An embodiment of the present invention includes a level-shifting signal buffer that contains a totem pole arrangement of MOS transistors connected to an output thereof and a control circuit that drives the totem pole arrangement of MOS transistors in a preferred manner so that signals across the MOS transistors will not exceed limits that may seriously damage the MOS transistors. A preferred signal buffer may include a PMOS pull-up transistor and an NMOS pull-down transistor arranged within a transistor totem pole. This transistor totem pole extends between a first power supply signal line that receives a first power supply signal (e.g., Vddext) and a reference signal line that receives a reference signal (e.g., GND). The PMOS pull-up transistor may be configured to support a maximum gate-to-drain voltage which is less than a difference in voltage between the first power supply signal and the reference signal. The control circuit, which is responsive to a data input signal, drives gate electrodes of the PMOS pull-up transistor and the NMOS pull-down transistor with signals that cause an output of the transistor totem pole to swing rail-to-rail from a voltage of the first power supply signal line to a voltage of the reference signal line during a pull-down time interval, while simultaneously maintaining a gate-to-drain voltage of the PMOS pull-down transistor within the maximum gate-to-drain voltage throughout the pull-down time interval.
An additional embodiment includes a level-shifting signal buffer comprising a CMOS inverter configured as a first totem pole arrangement of at least two PMOS transistors connected in series between a first power supply signal line and an output of the CMOS inverter and at least two NMOS transistors connected in series between the output and a reference signal line. A control circuit is also provided that drives the gate electrodes of the at least two PMOS transistors and the at least two NMOS transistors, in response to a data input signal (IN), a first bias signal (PG) having a magnitude that sets a minimum voltage to which a gate electrode of one of the at least two PMOS transistor is driven, a first power supply signal (Vddext) on the first power supply signal line and a second power supply signal (Vddint) having a magnitude less than a magnitude of the first power supply signal. The magnitude of the first bias signal (PG) may vary as a function of the magnitude of the first power supply signal.
According to this embodiment, the first bias signal (PG) has a magnitude that sets a first minimum voltage to which a gate electrode of an uppermost PMOS transistor in the CMOS inverter is driven and also sets a second minimum voltage to which a gate electrode of a lowermost PMOS transistor in said CMOS inverter is driven. The control circuit may comprise a first PMOS bias transistor and the first minimum voltage may equal a sum of the magnitude of the first bias signal (PG), a magnitude of a threshold voltage (VTP) of the first PMOS transistor and a magnitude of a reference signal on the reference signal line. The control circuit may also comprise a second PMOS bias transistor and the second minimum voltage may equal a sum of the magnitude of the first bias signal, a magnitude of a threshold voltage of the second PMOS transistor and a magnitude of a reference signal on the reference signal line. The uppermost PMOS transistor and the lowermost NMOS transistor in the CMOS inverter may also be driven by respective inverters. In particular, a first inverter may be provided that is powered by the first power supply signal and has an output electrically coupled to a gate electrode of the uppermost PMOS transistor. The first inverter may be driven by a level shift circuit that is responsive to the data input signal and first and second bias signals (PG and NG). A second inverter may also be provided that is powered by the second power supply signal and has an output electrically coupled to a gate electrode of a lowermost NMOS transistor.
A preferred level shift circuit comprises a second totem pole arrangement of two PMOS and two NMOS transistors arranged in an alternating sequence with a lowermost NMOS transistor and an uppermost PMOS transistor. The level shift circuit also comprises a pair of cross-coupled PMOS transistors, with a gate electrode of one of the PMOS transistors in the cross-coupled pair being electrically connected to a gate electrode of the uppermost PMOS transistor in the second totem pole. One of the PMOS transistors in the second totem pole is responsive to the first bias signal (PG) and is positioned within a pull-down path therein and one of the NMOS transistors in the second totem pole is responsive to the second bias signal (NG). The level shift circuit may also include a third totem pole arrangement of two PMOS and two NMOS transistors arranged in an alternating sequence and a fourth totem pole arrangement of two PMOS and two NMOS transistors arranged in an alternating sequence, with both the third and fourth totem poles having a lowermost NMOS transistor and an uppermost PMOS transistor. Based on this configuration, the lowermost NMOS transistor in the third totem pole may be responsive to a complementary data input signal ({overscore (IN)}) and the lowermost NMOS transistor in the fourth totem pole may be responsive to the data input signal (IN).